The present invention relates to a small-area, high-speed, low power consumption logic circuit which includes combined pass transistor and CMOS circuits, and also to a method of synthesizing from a Boolean function a small-area, high-speed, low power consumption logic circuit which includes combined pass transistor and CMOS circuits.
In a pass transistor logic circuit as one of logic circuits, a single transistor may have various logical functions. Thus, many researches are published which aim to fabricate pass transistor logic circuits well and replace all the conventional CMOS logic circuits with the pass logic circuits to obtain an LSI, while greatly reducing the number of transistors of the LSI to reduce its area and power consumption.
One of the researches discloses a method of synthesizing a pass transistor logic circuit having an intended logical faculty by replacing a respective one of nodes of a binary decision diagram produced from a Boolean function with a 2-input, 1-output, 1-control input pass transistor selector.
The binary decision diagram is a graphic representation of a Boolean function with a binary tree of nodes having two branches called branches xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d. It is capable of expressing a complicated Boolean function concisely. Thus, this is watched as a method of synthesizing a compact pass transistor logic circuit which has an intended logical function with fewer transistors than the conventional transistor logic circuit.
For example, Proceeding of IEEE 1994 Custom Integrated Circuits Conference, pp. 603-606 (hereinafter referred to as xe2x80x9cdocument 1xe2x80x9d) proposes a method of synthesizing a desired pass transistor logic circuit by fabricating a 2-input, 1-output pass transistor selector with n-channel field effect transistors alone, and inserting buffer inverters to reduce a delay time as requested.
The conventional CMOS logic circuit requires as many low-performance p-channel field effect transistors as n-channel field effect transistors. However, the great part of the pass transistor logic circuit synthesized by the method described in the document 1 can be composed of higher-performance n-channel field effect transistors alone excluding buffer inverters. Thus, a high-performance circuit is obtained which is reduced in area, delay time and power consumption compared to the conventional CMOS logic circuit.
IEEE Symposium on Low Power Electronics, 1995, pp.14-15 (hereinafter referred to as xe2x80x9cdocument 2xe2x80x9d) proposes a method which includes further development of the method of document 1. The method of document 2 is characterized in that a pass transistor logic circuit is synthesized on the basis of multi-level binary decision diagram, which is produced in the following process:
(1-1) A binary decision diagram is created from a Boolean function; and
(1-2) Partial trees which have different nodes indicated by a branch xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d, but which are exactly the same in graphic shape (the same-type partial trees) are extracted, and nodes controlled by the same-type partial tree are newly produced.
By beneficial effects of (1-2), a Boolean function is expressed with fewer nodes than a regular binary decision diagram in the multi-stage binary decision diagram. Thus, a pass transistor logic circuit having an intended logical function can be synthesized with fewer transistors than those described in document 1. Since the number of nodes connected in series is suppressed so that the number of stages of the synthesized pass transistor circuits is suppressed as well. Thus, a pass transistor logic circuit reduced in delay time, area and power consumption compared to that of document 1 can be synthesized.
Japanese Institute of Electronics, Information and Communication Engineers, technical report VLD 95-115, Vol. 95, No. 119, pp. 1-6 (hereinafter referred to as xe2x80x9cdocument 3xe2x80x9d) proposes a method of synthesizing a pass transistor logic circuit reduced in power consumption. In this method, like document 2, a pass transistor logic circuit is synthesized based on the multi-stage binary decision diagram. By using a minimum number of delay time improving buffer inverters, a pass transistor logic circuit of further reduced power consumption is synthesized.
JP-A-1-129611, JP-A-1-216622, JP-A-1-256219 and JP-A-7-130856 describe pass transistor circuits.
Furthermore, JP-A-7-168874 and JP-A-9-6821 describe a method of synthesizing a pass transistor logic circuit.
The inventors actually created binary decision graphs based on several Boolean functions and synthesized pass transistor logic circuits using the methods described in the documents 1, 2 and 3. As a result, for a certain Boolean function, a pass transistor logic circuit was successfully synthesized which was reduced greatly in the number of transistors, area, delay time and power consumption compared to the conventional CMOS logic circuits. However, for another Boolean function, we found that a pass logic circuit obtained conversely increased in area, delay time, and power consumption.
For example, when a simple 2-input NAND logic is synthesized with a pass transistor logic circuit, using each of the methods of the documents 1, 2 and 3, the logic circuit obtained is composed of six transistors shown by Cl in FIG. 4A. However, when it is synthesized with a CMOS logic circuit, the logic circuit obtained is a simplified circuit (C2 of FIG. 4A) composed of four transistors. When a 2-input NOR logic is synthesized with a pass transistor logic circuit, the resulting circuit contains six transistors (C3 of FIG. 4A), while when it is synthesized with a CMOS logic circuit, the resulting circuit contains four transistors (C4 of FIG. 4A).
As shown in FIGS. 4A-4C, for NAND logic and NOR logic, a circuit composed of CMOS gates has better performance with reference to area and delay time excluding power consumption than that composed of a pass transistor logic circuit As just described above, the pass transistor selector circuit is not suitable for the NAND or NOR logic, but suitable for a selector logic which selects one of signals using another signal because of its circuit composition. The NAND/NOR logic is a basic circuit of the CMOS circuit, so that it is natural that the CMOS circuit can fabricate a higher-performance logic circuit than the pass transistor circuit. However, even in NAND and NOR logics, the pass transistor circuit is lower in power consumption than the CMOS circuit.
This point is overlooked in the researches of the conventional pass transistor circuits, which indicates that the pass transistor circuit and CMOS circuits have their strongest and weakest points and that the pass transistor circuits are not always superior to the CMOS circuits in every respect. Which of the pass transistor circuits and the CMOS circuits is superior to the other varies depending on a preferentially handled one of area, delay time and power consumption as the circuit characteristic of a logic circuit to be synthesized.
Unlike the age in which the logic circuits were designed by peopleos hands, logic circuits are designed, using a high-class language such as HDL (Hardware Description Language) at present. Thus, it is very important how a logic composed of combined If-Then-Else (corresponding to a selector logic) and Boolean algebra is realized, using a compact logic circuit.
As described above, for any logic, or when any one of area, delay time and power consumption as the circuit characteristics takes preference over the others characteristics, a logic circuit having excellent circuit characteristics cannot be composed only of pass transistor circuits. Thus, a pass transistor/CMOS collaborated logic circuit is required to be produced which includes a well combination of advantages of pass transistor circuits and CMOS circuits so that the pass transistor circuits and CMOS circuits cooperate well with each other. In order to produce an excellent-performance LSI chip reduced in area, delay time, and power consumption, it has a very important significance to provide a method of automatically synthesizing in a computer system a pass transistor/CMOS collaborated logic circuit having such excellent performance.
When a pass transistor logic circuit was synthesized on the basis of a multi-level binary decision diagram, using the method described in the document 2, the number of transistors used was further reduced. However, some delay times conversely increased depending on logics employed. Our original analysis of those time delays clarified the existence of the following problem. A pass transistor logic circuit synthesized on the basis of its multi-level binary decision diagram includes a circuit in which a particular pass transistor selector is connected via a buffer inverter to a control input of a subsequent pass transistor selector. In this case, we found that a buffer inverter was connected in series with an inverter of the subsequent pass transistor selector, so that the delay time would increase inevitably. When the requirements of the delay time were strict, we found that the method of synthesizing the pass transistor logic circuit on the basis of the multi-level binary decision diagram was unpractical as the case may be because the delay time was a bottleneck.
It is an object of the present invention to provide a pass transistor/CMOS collaborated logic circuit more excellent in circuit characteristic which is area, delay time or power consumption than a logic circuit composed only of conventional pass transistors or CMOS transistors, and a method of automatically synthesizing such pass transistor/CMOS collaborated logic circuit in a computer system.
Another object of the present invention is to provide a pass transistor/CMOS collaborated logic circuit composed of a reduced number of transistors and reduced in delay time, and excellent in circuit characteristic which is area, delay time or power consumption, and a method of synthesizing such pass transistor/CMOS collaborated logic circuit, by solving the problem of the delay time with the conventional logic circuits synthesized only with pass transistors on the basis of the conventional multi-level binary decision diagram.
A further object of the present invention is to provide a method of synthesizing a logic circuit preferable in circuit characteristic which is area, delay time or power consumption or their combinations, by combining pass transistor circuits and CMOS circuits well.
In order to achieve the above objects, according to a desired aspect of the present invention, there is provided a logic circuit including a selector logic with a Boolean processing function, comprising:
a first p-channel field effect transistor (TP1) having a gate which is controlled by a first input (INI) thereto, and a source-drain path which is connected across a first operating potential (VDD) and a first node (NP1);
a second p-channel field effect transistor (TP3) having a gate which is controlled by a second input (IN2) thereto, and a source-drain path which is connected across the first operating potential (VDD) and the first node (NP1);
a first n-channel field effect transistor (TN1) having a gate which is controlled by the first input (IN1) thereto, and a source-drain path which is connected across the first node (NP1) and a fourth node (NP4);
a second n-channel field effect transistor (TN1) having a gate which is controlled by a second input (TN2) thereto, and a source-drain path which is connected across the fourth node (NP4) and a second operating potential (GND);
a third p-channel field effect transistor (TP3) having a gate which is controlled by the first node (NP1), and a source-drain path which is connected across the first operating potential (VDD) and a second node (NP2);
a third n-channel field effect transistor (TN3) having a gate which is controlled by the first node (NP1), and a source-drain path which is connected across the second node (NP2) and the second operating potential (GND);
a fifth n-channel field effect transistor (TN5) having a gate which is controlled by the second node (NP2), and a source-drain path which is connected across a third input (IN3) thereto and the third node (NP3);
a sixth n-channel field effect transistor (TN6) having a gate which is controlled by the first node (NP1), and a source-drain path which is connected across a fourth input (IN4) and the third node (NP3);
a fourth p-channel field effect transistor (TP4) having a gate which is controlled by the third node (NP3), and a source-drain path which is connected across the first operating potential (VDD) and a first output (OUT1); and
a fourth n-channel field effect transistor (TN4) having a gate which is controlled by the third node (NP3), and a source-drain path which is connected across the first first output (OUT1) and the second operating potential (GND) (FIG. 1).
According to another desired aspect, there is provided a logic circuit including a selector logic with a Boolean processing function, comprising:
a tenth p-channel field effect transistor (TP10) having a gate which is controlled by a tenth input (IN10) thereto, and a source-drain path which is connected across a first operating potential (VDD) and a tenth node (NP10);
a tenth n-channel field effect transistor (TN10) having a gate which is controlled by the tenth input (IN10), and a source-drain path which is connected across the tenth node (NP10) and the second operating potential (GND);
an eleventh n-channel field effect transistor (TN11) having a gate which is controlled by the tenth node (NP10), and a source-drain path being connected across an eleventh input (IN1) thereto and an eleventh node (NP11);
a twelfth n-channel field effect transistor (TN12) having a gate being controlled by the tenth input (IN10), and a source-drain path being connected across a twelfth input (IN12) and the eleventh node (NP11);
a fifteenth p-channel field effect transistor (TP15) having a gate which is controlled by the eleventh node (NP11), and a source-drain path which is connected across the first operating potential (VDD) and a twelfth node (NP12);
a fifteenth n-channel field effect transistor (NP15) having a gate which is controlled by the eleventh node (NP11), and a source-drain path which is connected across the twelfth node (NP12) and the second operating potential (GND);
a fourteenth p-channel field effect transistor (TP14) having a gate which is controlled by the twelfth node (NP12), and a source-drain path which is connected across the first operating potential (VDD) and a tenth output (OUT10);
a fourteenth n-channel field effect transistor (TN14) having gate which is controlled by the twelfth node (NP12), and a source-drain path which is connected across the tenth output (OUT10) and a thirteenth node (NP13);
a thirteenth p-channel field effect transistor (TP13) having a gate which is controlled by a thirteenth input (IN13) thereto, and a source-drain path which is connected across the first operating potential (VDD) and the tenth output (OUT10); and
a thirteenth n-channel field effect transistor (TN13) having a gate which is controlled by the thirteenth input (IN13), and a source-drain path which is connected across the thirteenth node (NP13) and the second operating potential (GND) (FIG. 2).
According to still another desired aspect of the present invention, there is provided a logic circuit including a selector logic with a Boolean processing function, comprising:
a twentieth p-channel field effect transistor (TP20) having a gate which is controlled by a twentieth input (IN20) thereto, and a source-drain path being connected across a first operating potential (VDD) and a twentieth node (NP20);
a twenty-first p-channel field effect transistor (TP21) having a gate which is controlled by a twenty first input (IN21) thereto, and a source-drain path which is connected across the first operating potential (VDD) and the twentieth node (NP20);
a twentieth n-channel field effect transistor (TN20) having a gate which is controlled by the twentieth input (IN20), and a source-drain path which is connected across the twentieth node (NP20) and a twenty-fourth node (NP24);
a twenty-first n-channel field effect transistor (TN21) having a gate which is controlled by the twenty-first input (TN21), and a source-drain path which is connected across the twenty-fourth node (NP24) and a second operating potential (GND);
a twenty-second p-channel field effect transistor (TP22) having a gate which is controlled by a twenty-second input (TN22) thereto, and a source-drain path which is connected across the first operating potential (VDD) and a twenty-second node (NP22);
a twenty-second n-channel field effect transistor (TN22) having a gate which is controlled by the twenty-second input (IN22), and a source-drain path which is connected across the twenty-second node (NP22) and the second operating potential (GND);
a twenty-third n-channel field effect transistor (TN23) having a gate which is controlled by the twenty-second node (IN22), and a source-drain path being connected across a twenty-third input (IN23) thereto and a twenty-third node (NP23);
a twenty-fourth n-channel field effect transistor (TN24) having gate which is controlled by the twenty-second input (IN22), and a source-drain path which is connected across the twentieth node (NP20) and the twenty-third node (NP23);
a twenty-fifth p-channel field effect transistor (TP25) having a gate which is controlled by the twenty-third node (NP23), and a source-drain path which is connected across the first operating potential (VDD) and a twentieth output (OUT20); and
a twenty-fifth n-channel field effect transistor (TN25) having a gate which is controlled by the twenty-third node (NP23), and a source-drain path which is connected across the twentieth output (OUT20) and the second operating potential (GND) (FIG. 3).
In order to synthesize, in a computer system, such logic circuit which includes combined pass transistor and CMOS logic circuits, in the present invention, a binary decision diagram or a multi-level decision diagram is created from a Boolean function. All nodes of the diagram are mapped into 2-input, 1-output, 1-control input pass transistor selectors to produce a pass transistor logic circuit. In the pass transistor logic circuit, a pass transistor selector operating as a NAND or NOR (or AND or OR) logic with any one of its two inputs being fixed to a logic constant xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is replaced with a CMOS gate operating as a NAND or NOR (or AND or OR) logic logically equivalent to the pass transistor selector if a calculated value of the area, delay time or power consumption as a predetermined circuit characteristic of a circuit resulting from the replacement is closer to an optimal value. The above processes are performed on all other pass transistor selectors to thereby synthesize a pass transistor/CMOS collaborated logic circuit whose predetermined circuit characteristic is optimal. As the circuit characteristics used for such optimization, there are, for example, area, delay time or power consumption, or a combination of two or three of them.
According to another desired aspect of the present invention, a binary decision diagram or a multi-level binary decision diagram is created from a Boolean function. Nodes of the diagram, having a pair of branches xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d only any one of which branches is fixed to a logical constant xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d, are mapped by CMOS gates equivalent in NAND or NOR (or AND or OR) logic to those nodes, and other nodes are mapped by corresponding pass transistor selector circuits having a two-input and one-output to thereby synthesize a pass transistor/CMOS collaborated logic circuit.